| 摘要 |
A circuit comprises a first plurality of transistors of a first channel length disposed along a speedpath, the first plurality of transistors providing a first timing performance. The circuit also comprises a second plurality of transistors of a second channel length having an expected equivalent functionality as the first plurality of transistors and disposed in parallel with the first plurality of transistors along the speedpath, wherein the second channel length is different from the first channel length. In addition, the circuit comprises an element configured to selectively replace the first plurality of transistors with the second plurality of transistors in response to a determination that the first timing performance of the first plurality of transistors fails a timing requirement of the speedpath. In one embodiment, the second channel length is a sub-minimal geometry with respect to the first channel length.
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