| 摘要 |
PURPOSE: A cycle slip detection for a timing recovery is provided to digitalize a timing recovery control loop completely by using a cycle slip correction technology. CONSTITUTION: In cycle slip detection for a timing recovery, an equalizer PREQ(partial response equalizer) is built in a interpolated timing recovery loop. A symbol detector is replaced with a partial response level detector. A re-sampling timing of the interpolator(IP) is adjusted by a digital phase-lock loop including a timing error detector(TED), a loop filter(LF), and an oscillator(NCO). Cycle slips are corrected by an FIFO memory. The cycle slip detector(CSD) is connected to the loop filter of the control loop to recover timing. The cycle slip detector includes an average timing error key generator generating average timing error keys from a filtered timing error signal of the loop filter. An output of the average timing error key generator is connected to a first comparator, which is connected to an accumulator. |
