| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a memory controller that can reconcile the minimization of the number of connected signal lines and a higher throughput. Ž<P>SOLUTION: A memory controller for controlling a plurality of memories which time-share an address and data expresses addresses of a data bus width not less than that of a first memory by the data bus bit of a second memory, expresses addresses of a data bus width not less than that of the second memory by the data bus bit of the first memory, and concurrently accesses the plurality of memories. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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