| 摘要 |
In a protection circuit for protecting semiconductor integrated circuit devices from an electrostatic breakdown or a latch-up due to an external surge, etc, a drain terminal of a PMOS transistor MP1, having a source terminal connected to a power supply VDD and a gate terminal receiving a control signal VG1 which a control circuit 2 generates on the basis of a power supply GND, is connected to one end of a resistor R1, having the other end connected to the power supply GND, and to a gate terminal of an NMOS transistor MN1 having a drain terminal and a source terminal connected to the power supply VDD and the power supply GND, respectively, and outputs an internal signal VG2 to the gate terminal of the NMOS transistor. When a predetermined voltage or more is applied to the power supply, the power supply is short-circuited.
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