| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a processing circuit whose circuit area is reduced while maintaining processing capability. <P>SOLUTION: The processing circuit includes: a register 11 for entering a parallel signal (plane text) of 128 bit width, and for executing processing in parallel for whole 128 bit width synchronously with a clock CLK_G of a low speed from a frequency-divider 10; a shift rows arithmetic unit 13; a mix columns arithmetic unit 14; an add round key arithmetic unit 15; a register 16; and a sub-byte arithmetic unit 12 with a shared type S-Box for executing processing synchronously with a clock CLK_L whose speed is higher than that of the clock CLK_G by 128/N bit width unit when dividing 128 bit width into N for making the shared type S-Box repeat the processing several times by dividing a parallel signal of 128 bit width into 128/N bit width. <P>COPYRIGHT: (C)2010,JPO&INPIT |
