发明名称 DATA RELAY CIRCUIT AND IMAGE PROCESSING APPARATUS
摘要 <p><P>PROBLEM TO BE SOLVED: To provide a data relay circuit for relaying data between two devices, that is used even when two clock frequencies for use in respective devices are different from each other and when one of them is high, and to provide an image processing apparatus using the same. <P>SOLUTION: A read timing setting part 27 is provided, which sets a time shorter than a delay time by which the write start is delayed behind a synchronizing timing, by a first time as a read delay time when a read frequency is higher than a write frequency, and sets a time longer than the delay time by a second time, as a read delay time when a read frequency is lower than a write frequency, and outputs data stored in a dual port memory 21 to a data receiving device sequentially in the storage order synchronously with a read clock signal after the lapse of the read delay time from the synchronizing timing. <P>COPYRIGHT: (C)2010,JPO&INPIT</p>
申请公布号 JP2009253375(A) 申请公布日期 2009.10.29
申请号 JP20080095371 申请日期 2008.04.01
申请人 KYOCERA MITA CORP 发明人 NISHIDA ATSUSHI
分类号 H04N1/00;G03G21/14;G06F3/12 主分类号 H04N1/00
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