NON-VOLATILE MEMORY BITCELL

摘要

A non-volatile memory bitcell which comprises a first bistable cantilever module and a second bistable cantilever modules. The bistable cantilever modules have a shared output terminal and each has an input terminal and two actuating terminals. The first and second cantilever modules are arranged such that their states are complementary. The memory bitcell further includes buffering means arranged to prevent the flow of current from the shared output terminal and further arranged to indicate the states of the first and second cantilever modules.