发明名称 Semiconductor memory device and method of performing data reduction test
摘要 A semiconductor device includes a plurality of package terminals included in a package, a plurality of chips provided on the package, each of the chips including a memory cell array and a plurality of data input/output terminals, and a plurality of data line control switch disposed between the plurality of package terminals and the plurality of data input/output terminals. The plurality of data line control switches of each of the chips connects the data input/output terminals of each of the chips to corresponding ones of the plurality of package terminals in a normal mode. The plurality of data line control switches connects different groups of the data input/output terminals in different ones of the chips to respective groups of the package terminals in a test mode. The respective groups of the data input/output terminals belong to the plurality of data input/output terminals. The respective groups of the package terminals are different between different ones of the chips.
申请公布号 US2009268498(A1) 申请公布日期 2009.10.29
申请号 US20090385949 申请日期 2009.04.24
申请人 ELPIDA MEMORY, INC. 发明人 NOMURA HIDEO;HAYASHI TOMONORI;SUGIYAMA YUJI
分类号 G11C5/02;G11C5/06;G11C7/00;H01L23/48 主分类号 G11C5/02
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