发明名称 |
METHOD OF CIRCUIT POWER TUNING THROUGH POST-PROCESS FLATTENING |
摘要 |
A method is provided for optimizing a hierarchical circuit design containing at least one reused cell. A first optimization is performed on the circuit design to meet a first objective. The first optimization is subject to a first constraint that all instances of the at least one reused cell are kept identical. The at least one reused cell is uniquified. A second optimization is performed to meet a second objective allowing uniquified instances of the at least one reused cell to be independently modified. The second optimization is subject to a second constraint that the first objective remains met.
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申请公布号 |
US2009271746(A1) |
申请公布日期 |
2009.10.29 |
申请号 |
US20080111574 |
申请日期 |
2008.04.29 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DRAPA MARK D. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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