MULTIPROCESSING CIRCUIT WITH CACHE CIRCUITS THAT ALLOW WRITING TO NOT PREVIOUSLY LOADED CACHE LINES

摘要

Data is processed using a first and second processing circuit (12) coupled to a background memory (10) via a first and second cache circuit (14, 14') respectively. Each cache circuit (14, 14') stores cache lines, state information defining states of the stored cache lines, and flag information for respective addressable locations within at least one stored cache line. The cache control circuit of the first cache circuit (14) is configured to selectively set the flag information for part of the addressable locations within the at least one stored cache line to a valid state when the first processing circuit (12) writes data to said part of the locations, without prior loading of the at least one stored cache line from the background memory (10). Data is copied from the at least one cache line into the second cache circuit (14') from the first cache circuit (14) in combination with the flag information for the locations within the at least one cache line. A cache miss signal is generated both in response to access commands addressing locations in cache lines that are not stored in the cache memory and in response to a read command addressing a location within the at least one cache line that is stored in the memory (140), when the flag information is not set.