发明名称 MEMORY CONTROL APPARATUS AND METHOD OF CONTROLLING THE SAME
摘要 <P>PROBLEM TO BE SOLVED: To provide efficient data transfer with a smaller number of buffers. Ž<P>SOLUTION: A write control part 51 write data input from any of an input port 41<SB>1</SB>to an input port 41<SB>3</SB>in an unused buffer among a buffer 61<SB>1</SB>to a buffer 61<SB>4</SB>, a read control part 53 can achieve efficient data transfer with a smaller number of buffers by reading the data written in the unused buffer among the buffer 61<SB>1</SB>to the buffer 61<SB>4</SB>to a specified output port to be an output destination among an output port 43<SB>1</SB>to an output port 43<SB>3</SB>. The present invention is applicable to a memory control apparatus for performing memory control. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2009252128(A) 申请公布日期 2009.10.29
申请号 JP20080102104 申请日期 2008.04.10
申请人 SONY CORP 发明人 INOMATA NAOKI
分类号 G06F13/38 主分类号 G06F13/38
代理机构 代理人
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