| 摘要 |
<p>A multilayer wiring, a semiconductor device, a substrate for display and a display, in which the area for placing a wiring layer can be narrowed while suppressing deterioration of characteristics resulting from the parasitic capacitance. The multilayer wiring comprises, from the substrate side, a first conductor located on the (n+1)th conductor layer, a second conductor located on the (n+2)th conductor layer and connected electrically with a conductor located below the (n+1)th conductor layer at least through a first contact hole in the (n+1)th insulating film directly under the (n+2)th conductor layer such that the second conductor does not overlap the first conductor in plan view of the major surface of the substrate, and a third conductor located on the (n+3)th conductor layer and connected electrically with the second conductor through a second contact hole in the (n+2)th insulating film directly under the (n+3)th conductor layer in plan view of the major surface of the substrate and placed on the first conductor side from second contact hole in the plan view of the major surface of the substrate.</p> |
