发明名称 WAFER LEVEL PACKAGE AND METHOD OF FABRICATING THE SAME
摘要 Wafer level packages and methods of fabricating the same are provided. In one embodiment, one of the methods comprises forming semiconductor chips having a connection pad on a wafer, patterning a bottom surface of the wafer to form a trench under the connection pad, patterning a bottom surface of the trench to form a via hole exposing the bottom surface of the connection pad, and forming a connecting device connected to the connection pad through the via hole. The invention provides a wafer level package having reduced thickness, lower fabrication costs, and increased reliability compared to conventional packages.
申请公布号 US2009267211(A1) 申请公布日期 2009.10.29
申请号 US20090498913 申请日期 2009.07.07
申请人 SAMSUNG ELECTRONICS CO., LTD. 发明人 CHUNG HYUN-SOO;LEE IN-YOUNG;HWANG SON-KWAN;LEE DONG-HO;HWANG SEONG-DEOK
分类号 H01L23/52;H01L23/48;H01L23/538 主分类号 H01L23/52
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