发明名称 METHOD OF FABRICATING VERTICAL TRANSISTOR IN HIGH INTEGRATED SEMICONDUCTOR DEVICE
摘要 PROBLEM TO BE SOLVED: To provide a method of fabricating a vertical transistor in a semiconductor device to prevent a cylindrical silicon pattern from collapsing due to a neck portion located at a bottom of the silicon pattern and to prevent a gate electrode from being etched due to misalignment in fabrication of the vertical transistor included in a semiconductor device. SOLUTION: The method of fabricating a semiconductor storage device relevant to fabrication of the vertical transistor includes steps of: etching a semiconductor substrate to form a pillar-type channel region pattern; forming a buried bit line in a bottom of the channel region pattern; forming a gate electrode pattern that surrounds the channel region pattern; forming a word line that connects to the gate electrode pattern; and forming a storage node over the channel region pattern and the gate electrode pattern. COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2009253273(A) 申请公布日期 2009.10.29
申请号 JP20080334529 申请日期 2008.12.26
申请人 HYNIX SEMICONDUCTOR INC 发明人 KIM JIN SOO
分类号 H01L21/8242;H01L27/108;H01L29/78 主分类号 H01L21/8242
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