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发明名称
METHOD AND APPARATUS FOR DESIGNING INTEGRATED CIRCUIT LAYOUTS
摘要
申请公布号
EP1759321(A4)
申请公布日期
2009.10.28
申请号
EP20050740549
申请日期
2005.04.29
申请人
CADENCE DESIGN SYSTEMS, INC.
发明人
SCHEFFER, LOUIS, K.;TEIG, STEVEN
分类号
G06F17/50;G03F1/36
主分类号
G06F17/50
代理机构
代理人
主权项
地址
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