ESD protection circuit and method for lowering capacitance of the ESD protection circuit

摘要

An electrostatic discharge (ESD) protection circuit and a method for reducing capacitance in the ESD protection circuit. A pair of gated diodes are connected in series, wherein the anode of one of the gated diodes is coupled to a lower voltage supply node and the cathode the other gated diode is connected to the upper voltage supply node. The commonly connected anode and cathode of the series connected gated diodes are connected to an input/output pad and to receiver and driver circuitry. The gates of the gated diodes are connected together. A gate biasing circuit is connected to the gates of the gated diodes. The gate biasing circuit applies a voltage to the gates of the gated diodes and depletes their channel regions of charge carriers, which lowers the capacitances of each gate diode.