发明名称 On-chip circuitry for bus validation
摘要 Systems, methodologies, media, and other embodiments associated with validating a bus are described. One exemplary system embodiment includes an integrated circuit operably connectable to a bus, the bus being connectable to an external device configured to drive one or more electrical signals onto the bus. The integrated circuit may comprise a first logic configured to receive a test sequence of electrical signals from the bus, a second logic configured to produce a check sequence of electrical signals related to the test sequence of electrical signals, and a compare logic operably connected to the first logic and the second logic. The compare logic may be configured to determine whether the bus is correctly transmitting data based, at least in part, on comparing the test sequence and the check sequence.
申请公布号 US7610526(B2) 申请公布日期 2009.10.27
申请号 US20050041821 申请日期 2005.01.24
申请人 HEWLETT-PACKARD DEVELOPMENT COMPANY, L.P. 发明人 SHERLOCK DEREK A.;DESAI JAYEN J.;CHEN CHIH-JEN
分类号 G01R31/28;G06F11/00 主分类号 G01R31/28
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