发明名称 CLAMP CIRCUIT AND ELECTRONIC DEVICE
摘要 <P>PROBLEM TO BE SOLVED: To provide a clamp circuit and an electronic device capable of protecting an internal circuit from abnormal voltage applied to an input terminal of an integrated circuit with less standby current. <P>SOLUTION: The clamp circuit 1 includes an NPN-type transistor 21 for leading current supplied from a current mirror circuit to a resistor element 22 connected to an input terminal 11. When the voltage of the input terminal 11 decreases to &le;0 V, the transistor 21 leads current through the resistor element 22, and the current mirror circuit leads current with the same current value through resistor elements 19, 20 for determining reference voltage of the clamp voltage. A flow of the current through the resistor elements 19, 20 further decreases the voltage of the input terminal 11, and when going below the clamp voltage, the transistor 21 can supply a base current to a transistor 14 to make it in conduction state in a moment. When the voltage of the input terminal 11 is above 0 V, the transistor 21 is in blocked condition and the standby current is 0. <P>COPYRIGHT: (C)2010,JPO&INPIT
申请公布号 JP2009246848(A) 申请公布日期 2009.10.22
申请号 JP20080093515 申请日期 2008.03.31
申请人 FUJITSU TEN LTD 发明人 KOBAYASHI YUSUKE;KOMATSU KAZUHIRO;KIDO KEISUKE;ENOMOTO DAISUKE
分类号 H03G11/02;H04N5/18 主分类号 H03G11/02
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