| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit capable of smoothly correcting a phase error of a sampling clock by timely and speedily detecting a frequency error by simple arithmetic processing. <P>SOLUTION: A phase error amount detected when a reproduced signal rises is supplied to a delay circuit 115 and a subtractor circuit 116. The subtractor circuit 116 subtracts the supplied phase error amount and the phase error amount supplied at the previous time (output from the delay circuit 115). On the basis of the result of this subtraction, an inclination value calculation circuit 117 calculates an inclination value Kp (frequency error) of a phase error amount on a time axis. Similarly, an inclination value calculation circuit 120 calculates an inclination value Kn based on a phase error amount detected when the reproduced signal falls. A control circuit 121 outputs a control signal when an inclination value Kp or Kn exceeds a threshold. A selector 111 supplies an LPF 112 with a ground signal in place of the phase error amount when the control signal is input. <P>COPYRIGHT: (C)2010,JPO&INPIT |
