| 摘要 |
PROBLEM TO BE SOLVED: To accurately and easily specify a failed portion by detecting connection errors between external memories while taking latency into consideration. SOLUTION: An FPGA 10 writes a data signal in the external memory 20, reads the data signal, and compares a read timing to actually read the data signal from the external memory 20 with an expected timing to read the signal when the connection to the external memory is normal. Information about the comparison result is created. The connection to the external memory 20 is analyzed using the created information about the comparison result, and connection errors between the external memories 20 are detected. The detection results are output to the outside. COPYRIGHT: (C)2010,JPO&INPIT
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