| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide an output buffer circuit capable of suppressing generation of an erroneous operation signal in start-up of a power source. Ž<P>SOLUTION: The output buffer circuit 1 includes a timing adjusting circuit TA for generating a fourth signal G to be outputted to an output circuit 30 by delaying a phase of fall timing in start-up of a power source for a second signal D outputted from a second level converter 10b. The timing adjusting circuit TA includes a third level converter 10c for generating a third signal E that falls later than a first signal B of a first level converter 10a, and an OR circuit 42 for outputting to the output circuit 30 the fourth signal G having a result of logical OR operation of the third signal E and the second signal D. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
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