发明名称 PLL CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To maintain fixed PLL characteristics in a PLL circuit requiring a wide frequency range, and to simplify a configuration for maintaining fixed characteristics. Ž<P>SOLUTION: The PLL circuit has: a VCO 11; a variable frequency dividing circuit 12 for dividing the oscillation signal into 1/N frequencies; and a phase comparison circuit 13 for comparing the phase of the frequency divided signal with that of a reference signal. The PLL circuit also has: a charge pump circuit 14 for outputting a charge pump current ICP of which pulse width changes according to the phase difference between the frequency divided signal and the reference signal, from the comparison output of the phase comparison circuit 13; and a loop filter 15 for outputting voltage of which the level changes corresponding to the phase difference between the frequency divided signal and the reference signal while the charge pump current ICP is supplied and supplying the voltage to the VCO 11 as its control voltage. As a function of the oscillation frequency of the VCO 11 and a coefficient for setting a PLL band, a control circuit 22 for calculating the value of the charge pump current ICP for setting to the charge pump circuit 14 is provided. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2009246607(A) 申请公布日期 2009.10.22
申请号 JP20080089373 申请日期 2008.03.31
申请人 SONY CORP 发明人 MIURA KIYOSHI
分类号 H03L7/093;H04B1/26 主分类号 H03L7/093
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