| 摘要 |
A phase-locked loop (PLL) circuit configuration is implemented using a variety of methods and devices. According to one example embodiment, a low power configuration is determined for the PLL circuit which meets a set of desired phase-locked loop circuit characteristics. The PLL circuit (110) has a first frequency-divider (112, 119), a feedback-divider (118) and a fractional-N mode (111).
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