发明名称 Delay circuit
摘要 A delay circuit respectively delays rising and falling edges of an input signal. The delay circuit comprises first and second delay lines, a control circuit, and first and second logic circuits. The first delay line delays the first input signal the first delay time to output the first delay output signal. The second delay line delays the first input signal the second delay time to output the second delay output signal. The control circuit outputs the control signal according to the first input signal. The first logic circuit receives the first delay output signal and outputs the first output signal according to the control signal and the first input signal. The second logic circuit receives the second delay output signal and outputs the second output signal according to the control signal and the first input signal. The first and second delay times are different.
申请公布号 US7605630(B2) 申请公布日期 2009.10.20
申请号 US20070845594 申请日期 2007.08.27
申请人 NANYA TECHNOLOGY CORPORATION 发明人 CHENG WEN-CHANG
分类号 H03H11/26 主分类号 H03H11/26
代理机构 代理人
主权项
地址