发明名称 |
Store instruction ordering for multi-core processor |
摘要 |
A method and apparatus for minimizing stalls in a pipelined processor is provided. Instructions in an out-of-order instruction scheduler are executed in order without stalling the pipeline by sending store data to external memory through an ordering queue. |
申请公布号 |
US7606998(B2) |
申请公布日期 |
2009.10.20 |
申请号 |
US20040002728 |
申请日期 |
2004.11.30 |
申请人 |
CAVIUM NETWORKS, INC. |
发明人 |
ASHER DAVID H.;KESSLER RICHARD E.;LEE YEN |
分类号 |
G06F9/00 |
主分类号 |
G06F9/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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