发明名称 Dynamic clock switch mechanism for memories to improve performance
摘要 This invention improves cache operation by dynamically extending one state of a clock signal supplied to a cache on operation cycles when a cache fill operation will occur. The dynamic extension of the clock signal includes delaying the clock signal, forming a waveform toggling between states upon each predetermined state transition of the delayed clock signal, selecting the clock signal when this waveform has a first stage, and selecting the delayed clock signal when this waveform has a second state. Dynamic extension is prevented during a test mode. An apparatus of this invention uses a flip-flop and a multiplexer to produce the dynamically delayed clock.
申请公布号 US7606991(B2) 申请公布日期 2009.10.20
申请号 US20070695282 申请日期 2007.04.02
申请人 TEXAS INSTRUMENTS INCORPORATED 发明人 GUPTE AJIT DEEPAK;AGRAWAL AAKASH;GOLECHA ABHAY
分类号 G06F12/00 主分类号 G06F12/00
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