发明名称 |
Synchronous page-mode phase-change memory with ECC and RAM cache |
摘要 |
Phase-change memory (PCM) cells store data using alloy resistors in high-resistance amorphous and low-resistance crystalline states. The time of the memory cell's set-current pulse can be 100 ns, much longer than read or reset times. The write time thus depends on the write data and is relatively long. A page-mode caching PCM device has a lookup table (LUT) that caches write data that is later written to an array of PCM banks. Host data is latched into a line FIFO and written into the LUT, reducing write delays to the relatively slow PCM. Host read data can be supplied by the LUT or fetched from the PCM banks. A multi-line page buffer between the PCM banks and LUT allows for larger block transfers using the LUT. Error-correction code (ECC) checking and generation is performed for data in the LUT, hiding ECC delays for data writes into the PCM banks.
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申请公布号 |
US7606111(B2) |
申请公布日期 |
2009.10.20 |
申请号 |
US20070769324 |
申请日期 |
2007.06.27 |
申请人 |
SUPER TALENT ELECTRONICS, INC. |
发明人 |
LEE CHARLES C.;YU FRANK I-KANG;CHOW DAVID Q. |
分类号 |
G11C7/10 |
主分类号 |
G11C7/10 |
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