| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a cache controller that reduces memory fetch latency and guarantees the order of a fetch and a write instruction to the same address. <P>SOLUTION: The cache controller determines whether to adopt data acquired by a speculative fetch, which is a memory fetch request output before it becomes clear whether data requested by a CPU is cached, by monitoring a status of the speculative fetch and the time period that is the sum of the time period in which the output speculative fetch will reach a memory control part (MAC 2) and the time period in which a response to a data write instruction issued before the output of the speculative fetch to the same address as the speculative fetch will be returned on completion of writing to a memory (DIMM 3) specified by the data write instruction. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
