| 摘要 |
A method of fabricating a vertical transistor in a semiconductor device improves integration of the semiconductor device according to a design rule. After a semiconductor substrate is etched to form a buried bit line, a gate electrode pattern that surrounds a cylindrical channel region pattern of the vertical transistor is formed, thereby preventing damage to the gate electrode pattern due to an etching process. The gate electrode pattern surrounds the channel region pattern where a width is narrower than second source and drain regions. The second source and drain regions are then deposited over the channel region pattern and the gate electrode pattern. As a result, a neck-shaped channel region does not collapse due to the weight of the second source and drain regions.
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