Delay Lock Loop Circuit, Timing Generator, Semiconductor Test Device, Semiconductor Integrated Circuit, and Delay Amount Calibration Method

摘要

A method replaces a delay amount measurement in which an initially set value of a counter is determined by a technique which replaces measurement of a delay amount, whereby a time required for calibration of a delay circuit can be reduced. One counter set value of a plurality of counter set values is loaded, a delay lock loop circuit is switched to a lock mode, and a sequence circuit of a cycle slip detection circuit is reset. Thereafter, a cycle slip detection signal output from the sequence circuit is read, and on the basis of this cycle slip detection signal, it is judged whether or not an output signal of a delay circuit causes cycle slip. If the cycle slip is caused, the counter set value is switched. On the other hand, if any cycle slip is not caused, the counter set value is locked, thereby terminating the process.