LOOP TYPE CLOCK ADJUSTMENT CIRCUIT AND TEST DEVICE

摘要

Provided is a loop type clock adjustment circuit including: a variable delay circuit which applies a variable delay based on an analog signal to a reference clock so as to generate a delay clock; a phase detection unit which detects a phase difference between the delay clock and the reference clock so as to generate a phase difference signal having a level based on the phase difference; a counter which counts up or down in accordance with the phase difference signal level; and a digital/analog converter which converts the count value of the counter into an analog signal for supply to the variable delay circuit. The counter has: a first counter (22) which counts the least significant digit of the count value in accordance with the phase difference signal by using a first thermometer code; a second counter (24) which counts the most significant digit of the count value in accordance with the phase difference signal by using a second thermometer code; and a control circuit (26) which performs control so that a humming distance between the first counter (22) and the second counter (24) is 1 even in a carry operation or a borrow operation.