发明名称 METHOD FOR CONTROLLING FLATNESS OF WAFER IN DOUBLE SIDE POLISHING PROCESS
摘要 PURPOSE: A method for controlling flatness of a wafer in a double side polishing process is provided to manufacture a wafer of high quality by again performing a double side polishing process for a short time in case measured flatness is less than a reference value. CONSTITUTION: A double side polishing process about a wafer is performed for a first polishing time(S120). Flatness of the polished wafer is measured by using a wafer flatness measuring device(S130). In case the measured flatness of the wafer is less than a reference value, the double side polishing process about the wafer is performed for a second polishing time shorter than the first polishing time(S160). In case the measured flatness of the wafer reaches to the reference value, the double side polishing process about the wafer is finished.
申请公布号 KR20090108263(A) 申请公布日期 2009.10.15
申请号 KR20080033599 申请日期 2008.04.11
申请人 SILTRON INC. 发明人 LEE, CHANG HUN
分类号 H01L21/304 主分类号 H01L21/304
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