发明名称 |
MINIMIZING TRANSISTOR VARIATIONS DUE TO SHALLOW TRENCH ISOLATION STRESS |
摘要 |
The present invention provides, in one embodiment, a method of manufacturing a metal oxide semiconductor (MOS) transistor (100). The method comprises forming an active area (105) in a substrate (115), wherein the active area (105) is bounded by an isolation structure (120). The method further includes placing at least one stress adjuster (130) adjacent the active area (105), wherein the stress adjuster (130) is positioned to modify a mobility of a majority carrier within a channel region (155) of the MOS transistor (100). Other embodiments of the present invention include a MOS transistor device (200) and a process (300 ) for constructing an integrated circuit.
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申请公布号 |
US2009258468(A1) |
申请公布日期 |
2009.10.15 |
申请号 |
US20090489344 |
申请日期 |
2009.06.22 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
YOON JONG SHIK;KIM ANDREW TAE |
分类号 |
H01L21/762;G01R31/26;H01L21/336;H01L21/66;H01L21/76;H01L21/763;H01L21/8234;H01L21/8238 |
主分类号 |
H01L21/762 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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