发明名称 MANUFACTURING METHOD OF INTEGRATED CIRCUIT
摘要 <P>PROBLEM TO BE SOLVED: To solve the problem, in manufacturing of an integrated circuit, wherein the upper surface of a tungsten (W) plug recedes from the surface of a silicon oxide film, resulting in the lowering of coverage of a wiring formed thereon, when the plug is formed in a contact hole provided to the silicon oxide film. Ž<P>SOLUTION: After a contact hole 46 is formed on a silicon oxide film 44, a tungsten (W) film 48 is deposited. The W film 48 is etched back so that the upper surface of the silicon oxide film 44 is exposed, and a W plug 50 is formed in the contact hole 46. Here, the upper surface of the W plug 50 recedes from the surface of the silicon oxide film 44 due to over-etching on the W film 48, producing a step 30 between inside and outside of the contact hole 46. Before forming a wiring thereon, the silicon oxide film 44 is etched back to reduce the step 30 for flattening. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
申请公布号 JP2009238856(A) 申请公布日期 2009.10.15
申请号 JP20080080384 申请日期 2008.03.26
申请人 SANYO ELECTRIC CO LTD;SANYO SEMICONDUCTOR CO LTD 发明人 MATSUDA KATSUSHI
分类号 H01L21/768;H01L21/3205 主分类号 H01L21/768
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