发明名称 POWER AWARE ASYNCHRONOUS CIRCUITS
摘要 <p>Techniques are described for converting netlists for synchronous circuits such as combinational modules, flip flops (or latches), and clock gating modules, to netlist of asynchronous modules. Processes including algorithms are described that bundle multiple modules in an enable domain, so that they are activated only if the incoming enable token to the enable domain has the UPDATE value. The modules can be clustered inside an enable domain, so that each cluster has a separate controller. The objective function of bundling and clustering can minimize power consumption with respect to a given cycle time. Exemplary embodiments can include a gated multilevel domino template.</p>
申请公布号 WO2009126880(A2) 申请公布日期 2009.10.15
申请号 WO2009US40196 申请日期 2009.04.10
申请人 UNIVERSITY OF SOUTHERN CALIFORNIA;SHIRING, KEN;BEEREL, PETER, A.;LINES, ANDREW;SAIFHASHEMI, ARASH 发明人 SHIRING, KEN;BEEREL, PETER, A.;LINES, ANDREW;SAIFHASHEMI, ARASH
分类号 G06F17/50 主分类号 G06F17/50
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