| 摘要 |
A multi-processor system has a plurality of processor cores, a plurality of level-one caches, and a level-two cache. The level-two cache has a level-two cache memory which stores data, a level-two cache tag memory which stores a line bit indicative of whether an instruction code included in data stored in the level-two cache memory is stored in the plurality of level-one cache memories or not line by line, and a level-two cache controller which refers to the line bit stored in the level-two cache tag memory and releases a line in which data including the same instruction code as that stored in the level-one cache memory is stored, in lines in the level-two cache memory.
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