SYSTEM FOR INCREASING THROUGHPUT FOR MEMORY DEVICE

摘要

The present invention provides a system for increasing the throughput for a memory subsystem, in particular one that includes a pipelined memory device and a non-cached single-bus processor core. With this system, total latency, of the memory subsystem is reduced and thus throughput is increased, said condition is achieved with the introduction of at least two sliding window buffers within the memory controller of the present invention.