发明名称 |
INPUT CLOCK DETECTION CIRCUIT FOR POWERING DOWN A PLL-BASED SYSTEM |
摘要 |
An apparatus is provided for detecting the loss of an input clock signal for a phase-locked loop (PLL). The apparatus includes a time delay circuit, a first frequency divider and a digital logic circuit. The time delay circuit receives the input clock signal and outputs a first time-delayed clock signal. The first frequency divider receives an input signal from an internal clock of the PLL and outputs a clock signal having the same frequency or a lower frequency than that of the time-delayed clock signal. The digital logic circuit that receives the first frequency divider output signal and the first time-delayed clock signal and outputs a signal indicating the loss of the input clock signal if there is no first time-delayed clock signal for a cycle of the first frequency divider output signal.
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申请公布号 |
US2009256600(A1) |
申请公布日期 |
2009.10.15 |
申请号 |
US20090488989 |
申请日期 |
2009.06.22 |
申请人 |
INTEGRATED DEVICE TECHNOLOGY, INC. |
发明人 |
JING TAO |
分类号 |
H03L7/06 |
主分类号 |
H03L7/06 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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