| 摘要 |
<p>Disclosed is a memory control circuit in which the minimum activation interval time for different lines in the same SDRAM bank, the operating speed, and the number of banks are input to an access count setting circuit, the optimal number of read or write iterations for each bank is calculated, and a command sequence and addresses for reading or writing video signals to SDRAM are generated by a DRAM access control circuit.</p> |
