发明名称 Delay control circuit
摘要 <p>A first variable delay circuit delays an input signal, introduces a first delay into a first edge of the input signal, and generates a first delay signal. A second variable delay circuit delays the input signal, introduces a second delay into a second edge, and generates a second delay signal. A control circuit controls the first variable delay circuit and the second variable delay circuit such that the first delay and the second delay are identical. A generation circuit combines the first edge of the first delay signal and the second edge of the second delay signal, and generates a third delay signal.</p>
申请公布号 GB2436406(B) 申请公布日期 2009.10.14
申请号 GB20060014443 申请日期 2006.07.20
申请人 FUJITSU LIMITED;FUJITSU MICROELECTRONICS LIMITED 发明人 KATSUHIKO ARIYOSHI;SOUYOU SETSU;RYUSUKE OBARA
分类号 H03K5/131;H03K5/135;H03L7/06 主分类号 H03K5/131
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