| 摘要 |
A first object of the present invention is to reduce interrupt to a CPU which occurs when microprocessors that are connected by a network receive a packet from the network to efficiently operate the processors. A second object of the present invention is to provide a microprocessor and a communication method, which make it possible to reply a quick response to the microprocessor at the transmitting side. Each of the microprocessors includes the CPU and a communication module. The communication module includes a register that stores information which is managed by the microprocessor. The communication module compares information at a given bit position within the packet which is inputted through the network with information retained in the register, and determines whether a process corresponding to the packet reception is conducted by the CPU, or not, according to the comparison result.
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