发明名称 |
Various methods and apparatuses to preserve a logic state for a volatile latch circuit |
摘要 |
An apparatus for a volatile latch circuit. The volatile latch circuit may have a master latch sub circuit coupled to a slave latch sub circuit. The slave latch sub circuit maintains the logic state stored by the volatile latch circuit. The slave sub circuit may connect to a first power trace that continuously provides a first voltage potential to the slave latch sub circuit even during a sleep mode. The master latch sub circuit may connect to a second power trace that provides a second voltage potential to the master latch sub circuit that is switchably turned off during the sleep mode.
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申请公布号 |
US7603634(B2) |
申请公布日期 |
2009.10.13 |
申请号 |
US20060401806 |
申请日期 |
2006.04.10 |
申请人 |
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发明人 |
SLUSS GENE T.;SHERLEKAR DEEPAK D.;GHEEWALA TUSHAR R. |
分类号 |
G06F17/50 |
主分类号 |
G06F17/50 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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