发明名称 |
Method, apparatus and program product for enhancing performance of an in-order processor with long stalls |
摘要 |
A method, system, and computer program product for enhancing performance of an in-order microprocessor with long stalls. In particular, the mechanism of the present invention provides a data structure for storing data within the processor. The mechanism of the present invention comprises a data structure including information used by the processor. The data structure includes a group of bits to keep track of which instructions preceded a rejected instruction and therefore will be allowed to complete and which instructions follow the rejected instruction. The group of bits comprises a bit indicating whether a reject was a fast or slow reject; and a bit for each cycle that represents a state of an instruction passing through a pipeline. The processor speculatively continues to execute a set bit's corresponding instruction during stalled periods in order to generate addresses that will be needed when the stall period ends and normal dispatch resumes. |
申请公布号 |
US7603543(B2) |
申请公布日期 |
2009.10.13 |
申请号 |
US20050055862 |
申请日期 |
2005.02.11 |
申请人 |
INTERNATIONAL BUSINESS MACHINES CORPORATION |
发明人 |
DOOLEY MILES ROBERT;FROMMER SCOTT BRUCE;LE HUNG QUI;LEVENSTEIN SHELDON B.;SAPORITO ANTHONY |
分类号 |
G06F9/30 |
主分类号 |
G06F9/30 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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