发明名称 COLUMN DECODER OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE: A column decoder for a semiconductor integrated circuit is provided to reduce an unnecessary operational current of a main decoder by floating the first to eighth inverters and removing a current path. CONSTITUTION: A column decoder includes a controller(10), a pre-decoder(20), a pre-decoding signal transmitter(30), a first main decoder(41), and a second main decoder(42). The controller inactivates one of the first and second cell region activation signals in response to a cell region division signal. The first and second cell activation signals activate the first and second cell regions respectively. The pre-decoder decodes the column address and outputs the first pre-decoding signal group and the second pre-decoding signal group. The pre-decoding signal transmitter inactivates one of the first and second pre-decoding signal groups in response to the inactivation of one of the first and second cell region activation signals. The first and second main decoders receive the first and second pre decoding signal groups respectively. The first and second main decoders are stopped if the inputted signal group is not activated.
申请公布号 KR20090107362(A) 申请公布日期 2009.10.13
申请号 KR20080032838 申请日期 2008.04.08
申请人 HYNIX SEMICONDUCTOR INC. 发明人 PAKR, SUN HWA
分类号 G11C8/10;G11C7/10 主分类号 G11C8/10
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