发明名称 Dual-damascene process to fabricate thick wire structure
摘要 A method and semiconductor device. In the method, at least one partial via is etched in a stacked structure and a border is formed about the at least one partial via. The method further includes performing thick wiring using selective etching while continuing via etching to at least one etch stop layer.
申请公布号 US7602068(B2) 申请公布日期 2009.10.13
申请号 US20060275604 申请日期 2006.01.19
申请人 INTERNATIONAL MACHINES CORPORATION 发明人 COOLBAUGH DOUGLAS D.;DOWNES KEITH E.;LINDGREN PETER J.;STAMPER ANTHONY K.
分类号 H01L23/52 主分类号 H01L23/52
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