发明名称 |
LOCK DETECTION CIRCUIT FOR PHASE LOCKED LOOP |
摘要 |
A lock detector circuit for detecting a lock condition between a reference signal and a feedback signal includes a first counter for outputting a first counter value indicative of a number of clock cycles of the reference signal, and a second counter for outputting a second counter value indicative of a number of clock cycles of the feedback signal. An asynchronous comparator receives the first and second counter values and provides an output signal having a pulse width that is proportional to the difference between the first and second counter values. A pulse width detector receives the comparator output signal and produces an output signal that is indicative of the relationship between the pulse width of the comparator output signal and a predetermined threshold value. A state machine controls the state of at least one lock indication signal according to the pulse width detector output signal.
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申请公布号 |
US2009251226(A1) |
申请公布日期 |
2009.10.08 |
申请号 |
US20090416933 |
申请日期 |
2009.04.02 |
申请人 |
FREESCALE SEMICONDUCTOR, INC |
发明人 |
KATHURIA MANAN;ABHISHEK KUMAR;CHAKRAVARTY SUHAS;ROOPAK SURI |
分类号 |
H03L7/095 |
主分类号 |
H03L7/095 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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