| 摘要 |
<P>PROBLEM TO BE SOLVED: To provide a PLL circuit that shortens the lock time of a PLL. Ž<P>SOLUTION: A low-pass filter 107 constituting the PLL is applied with a maximum voltage of the circuit to be charged. In the process, a clock counter 102 counts the number of VCO output clocks in a single cycle of a reference clock 10, to estimate the phase difference at a lock point with respect to a reference clock and a frequency-divided clock of a VCO output clock 27 with the counted values at two predetermined points of time. Estimation is performed by an arithmetic processing circuit 105, based on the catalog data of a VCO alone, a counter load value 24 is calculated, so that a frequency-dividing counter 109 supplies it as a frequency-divided signal 28, and a phase comparator 106 supplies it as the estimated phase difference to the low-pass filter, after the charging. Ž<P>COPYRIGHT: (C)2010,JPO&INPIT Ž
|
