CACHE MEMORY DEVICE, CACHE MEMORY SYSTEM, AND PROCESSOR SYSTEM

摘要

Provided is a cache memory device that stores synchronization primitives and reduces the overhead associated with operating synchronization primitives. A cache memory device comprises a memory (1131A) that can associate and store data and attribute information, and a cache controller (1132A). The cache controller (1132A) obtains from a CPU (111A) a request signal requesting data access and an instruction signal indicating whether or not the requested data is a synchronization primitive, and when the data requested by the request signal is indicated as being a synchronization primitive by the instruction signal, the cache controller (1132A) associates the requested data with synchronization primitive attribute information indicating that the requested data is a valid synchronization primitive and stores in the memory (1131A). The cache controller (1132A) prohibits purging of data that corresponds to the synchronization primitive attribute information and is stored in the memory (1131A).