CLOCK AND DATA RECOVERY CIRCUIT WITH ELIMINATING DATA-DEPENDENT JITTERS

摘要

The present invention relates to a clock and data recovery circuit (CDR), and in particular, to a CDR circuit in a full digital scheme which cancels the data-dependent jitter. A DDJ cancellation circuit according to the present invention efficiently cancels the data-dependent jitter, making it possible to configure the reliable clock and data recovery circuit in the serial link data communication through the channel of the predetermined bandwidth.