| 摘要 |
<p><P>PROBLEM TO BE SOLVED: To provide a reset circuit capable of avoiding erroneous output of a reset cancellation signal when a supply voltage lower than a prescribed voltage rises, and to provide an IC for power supply control incorporating the reset circuit. <P>SOLUTION: The reset circuit has: a voltage comparison means (CMP0) for comparing voltage proportional to a supply voltage with a reference voltage; a first delay means (DLY1) for delaying detection timing for transmitting to a poststage, when the voltage comparison means detects that the supply voltage has become not less than prescribed potential; and a second delay means (DLY2) for delaying detection timing for transmitting to the poststage, when the voltage comparison means detects that the supply voltage has become not more than the prescribed potential. The second delay means has: a second determination circuit (INV3) determining the potential of a node inside the delay means according to a logic threshold; and pull up means (SW3, GT1) that are connected to the node and pull up the potential of the node when the supply voltage rises. <P>COPYRIGHT: (C)2010,JPO&INPIT</p> |
